Two cores ยท one RAM
RAM done: false ยท Core2 sees: false ยท spins: 0
๐ง Core 1 ยท Thread A
cachedone: false
done = true;
๐ง Core 2 ยท Thread B
cachedone: false
while (!done) { spin }spins: 0
๐ read hoisted into a register
๐พ Main memory (RAM)done: false