Two cores ยท one RAM RAM done: false ยท Core2 sees: false ยท spins: 0
๐Ÿง Core 1 ยท Thread A
cachedone: false
done = true;
๐Ÿง Core 2 ยท Thread B
cachedone: false
while (!done) { spin }spins: 0
๐ŸŒ€ read hoisted into a register
๐Ÿ’พ Main memory (RAM)done: false
๐Ÿ”€ Reordering order: as written
Thread A writes
โ‘  data = 42;
โ‘ก ready = true;
Thread B sees
data: 0 ยท ready: false
Thread B is spinning
B keeps reading done from its own cache. Press โ–ถ A: done = true.
โ–ธ volatile buys you visibility, not atomicity โ€” count++ is still a race.